The present invention relates to a semiconductor integrated circuit and to a level conversion circuit, and more particularly, for instance, to a technology which can be effectively used for an interface circuit for a semiconductor integrated circuit in which the amplitude of internal signals and that of external signals differ from each other.
According to the prior art, circuits for converting signals of a smaller amplitude into signals of a greater amplitude include, for instance, a level conversion circuit disclosed in Japanese Patent Laid-Open No. Hei 5 (1993)-343979, the circuit illustrated in FIG. 10. The circuit of FIG. 10 consists of an inverter INV0, having VDD (e.g. 1.5 V) as its source voltage, for inverting an input signal IN and a latch circuit LT, having VDD2 higher than VDD (e.g. 3.3 V) as its source voltage and the signal/IN resulting from inversion by the inverter and the pre-inversion signal IN. The latch circuit LT has a configuration comprising one CMOS inverter INV1 in which two p-channel MOSFETs Qp1 and Qp2 and one n-channel MOSFET Qn1 are connected in series and one CMOS inverter INV2 in which two p-channel MOSFETs Qp1 and Qp3 and one n-channel MOSFET Qn2 are connected in series, the output terminal of each inverter being connected to the gates of the MOSFETs Qp2 and Qp3 of the other inverter.
In the level conversion circuit of FIG. 10, when the input signal IN of 0 to 1.5 V in amplitude rises from a low level to a high level, the MOSFET Qn1 immediately shifts from an off-state to an on-state. As a result, its output signal OUT varies from VDD2, which may be 3.3 V for instance, to a ground potential (0 V), but when the input signal IN varies from a high level to a low level, only when the MOSFET Qn2 is turned on by the inverted signal/IN to vary the output of the inverter INV2 to a low level and the MOSFET Qp2 shifts from an off-state to an on-state, the output signal OUT varies from the ground potential (0 V) to VDD2, which may be 3.3 V.
For this reason, a level conversion circuit according to the prior art is slower in the variation of the output signal from a low level to a high level than in the variation from a high level to a low level. As a result, on the part of a circuit to receive a signal from such a level conversion circuit, the signal should be accepted at the later signal timing, resulting in the problems of more complex timing design and of a longer time taken by signal transmission, which impedes raising the system speed.
An object of the present invention is to provide a level conversion circuit whose output signal varies from a low level to a high level and from a high level to a low level substantially as fast.
Another object of the invention is to provide a semiconductor integrated circuit technology which makes it possible to raise the speed of signal transmission in a semiconductor integrated circuit having within it two signal transmission routes differing in amplitude.
Still another object of the invention is to make it possible to raise the speed of a system using a semiconductor integrated circuit having a level conversion circuit in its input/output (I/O) unit and forming and supplying a large amplitude signal on the basis of a narrow amplitude internal signal.
The above-noted and other objects and novel features of the invention will become more apparent from the description in this specification when taken in conjunction with the accompanying drawings.
What follows is a brief summary of typical aspects of the present invention disclosed in this application.
Thus, the configuration is such that a level conversion circuit is composed of a level shift circuit for supplying a level-converted signal in the same phase as the input signal and a signal in the reverse phase thereto and a follow-up circuit responsive to the earlier of the output signals of the level shift circuit for generating an output signal, wherein the follow-up circuit consists of an inverter circuit in which two p-channel type MOS transistors and two n-channel type MOS transistors are connected in series between a first voltage terminal and a second voltage terminal, of which one pair is used as input transistors and the remaining pair of transistors are subjected to control based on the output signal of the level shift circuit to be quickly responsive to the next variation.
A level conversion circuit according to a first aspect of the invention under the present application has a first circuit comprising a first input terminal for receiving a first signal having a first signal amplitude, a first output terminal for supplying a second signal having a second signal amplitude greater than the first signal amplitude and being in the same phase as the first signal, and a second output terminal for supplying a third signal having a second signal amplitude greater than the first signal amplitude and being in the phase reverse to the first signal; and a second circuit comprising a first p-channel type MOS transistor, a second p-channel type MOS transistor, a first n-channel type MOS transistor and a second n-channel type MOS transistor whose source-drain routes are connected in series between a first voltage terminal and a second voltage terminal and the drain of the first p-channel type MOS transistor and the drain of the n-channel type MOS transistor are connected to a third output terminal, wherein the second circuit forms a fourth signal having the second signal amplitude on the basis of the signal variation of the second signal supplied from the first output terminal of the first circuit or of the third signal supplied from the second output terminal of the first circuit, whichever is faster in signal level change, and supplying the fourth signal from the third output terminal.
The above-described means, as the second circuit forms an output signal on the basis of what is faster in signal level change out of the complementary signals supplied from the first circuit, the output signal can quickly vary not only at the leading edge but also the trailing edge of the input signal, and a signal having a small amplitude can be converted into one of a large amplitude and transmitted without sacrificing the signal transmission speed.
Preferably, a delay means may be provided to delay the second signal supplied from the first output terminal of the first circuit or the third signal supplied from the second output terminal of the first circuit to control the second p-channel type MOS transistor and the first n-channel type MOS transistor, or the first p-channel type MOS transistor and the second n-channel type MOS transistor. This results in shifting of the second circuit to a state in which it is more quickly responsive to the next signal change and thereby makes it possible to raise the signal transmission speed.
In a further proposed configuration, where a circuit from which, according to a signal inputted to the gate terminal of a MOS transistor, a signal matching the gate input signal is supplied to the source or drain terminal of the MOS transistor is defined to be one stage, the number of circuit stages which a signal reaching the third output terminal of the second circuit from the first input terminal of the first circuit via the second output terminal goes through and the number of circuit stages which a signal reaching the third output terminal of the second circuit from the first input terminal of the first circuit via the third output terminal goes through are equal. This substantially equalizes the lengths of time taken by the signal in the same phase as the input signal and the signal in the reverse phase to the input signal to reach the second circuit, enabling the output signal to quickly vary not only at the leading edge but also the trailing edge of the input signal and the transmission speed of signals having different amplitudes to be raised.
Further, the second circuit may be so configured that the state of the second p-channel type MOS transistor or the first n-channel type MOS transistor vary with any change in the second signal or the third signal supplied from the first circuit. This makes it possible to reduce the gate size of the second p-channel type MOS transistor or the first n-channel type MOS transistor, thereby alleviating the load on the preceding circuit and accelerate the variations of the second signal and the third signal.
In addition, a high resistance element for pull-up use and a high resistance element for pull-down use may be connected respectively in parallel to the first p-channel type MOS transistor and the second n-channel type MOS transistor. This enables the second circuit to have two logical thresholds, and the variation of the output signal to be further accelerated as the logical threshold drops when the input signal varies from a low level to a high level and rises when the input signal varies from a high to a low level.
The ratio between the gate width and the gate length of the first p-channel type MOS transistor may be set to be greater than the ratio between the gate width and the gate length of the second p-channel type MOS transistor, and the ratio between the gate width and the gate length of the second n-channel type MOS transistor is set to be greater than the ratio between the gate width and the gate length of the first n-channel type MOS transistor. This makes possible reducing the on-resistances of the first p-channel type MOS transistor and the second n-channel type MOS transistor which serve as resistive loads on the second p-channel type MOS transistor and the first n-channel type MOS transistor, contributing to further accelerating the variation of the output signal.
Further, a first inverter for logically inverting the first signal may be provided, and the first circuit may have a second input terminal for receiving the output signal of the first inverter and is configured of a third n-channel type MOS transistor and a fourth n-channel type MOS transistor whose gate terminals are connected respectively to the first input terminal and the second input terminal, a third p-channel type MOS transistor whose source-drain route is connected in series to the third n-channel type MOS transistor and to whose gate terminal is connected the drain terminal of the fourth n-channel type MOS transistor, and a fourth p-channel type MOS transistor whose source-drain route is connected in series to the fourth n-channel type MOS transistor and to whose gate terminal is connected the drain terminal of the third n-channel type MOS transistor, wherein the first output terminal is connected to the drain terminal of the fourth n-channel type MOS transistor, the second output terminal is connected to the drain terminal of the third n-channel type MOS transistor, and a second inverter for logically inverting the second signal is connected to the first output terminal. As this configuration causes the first circuit to receive the first signal and its inverted signal with the n-channel type MOS transistor and operates to vary the second signal and the third signal, which are its outputs, to a low level at high speed, the transmission of the variation of signals from the first circuit to the second circuit is accelerated.
Further, the second circuit may be so configured so that the state of the second p-channel type MOS transistor or the first n-channel type MOS transistor vary with a change in the second signal or the third signal supplied from the first circuit. This configuration makes it possible to reduce the gate size of the second p-channel type MOS transistor or the first n-channel type MOS transistor, thereby alleviating the load on the preceding circuit and accelerate the variations of the second signal and the third signal.
Also, a third inverter may be provided to control the first p-channel type MOS transistor and the second n-channel type MOS transistor according to the second signal supplied from the first output terminal of the first circuit or the output signal of the second inverter, whichever is slower in signal variation. This configuration makes it possible to shift the first p-channel type MOS transistor and the second n-channel type MOS transistor to an on/off state without delay after the fourth signal supplied from the second circuit varies and to prepare for the next signal variation.
Also, a delay means may be provided to control the second p-channel type MOS transistor and the first n-channel type MOS transistor or the first p-channel type MOS transistor and the second n-channel type MOS transistor according to the signal variation of the second signal supplied from the first output terminal of the first circuit or of the third signal supplied from the second output terminal of the first circuit, whichever is slower in signal variation. This configuration makes it possible to shift the first p-channel type MOS transistor and the second n-channel type MOS transistor or the first p-channel type MOS transistor and the second n-channel type MOS transistor to an on/off state without delay after the fourth signal supplied from the second circuit varies and to prepare for the next signal variation.
Further, the second circuit may as well be so configured as to cause the state of the first p-channel type MOS transistor or the second n-channel type MOS transistor in response to a variation of the second signal or the third signal supplied from the first circuit, whichever is faster. This results in a variation of the thresholds of the first p-channel type MOS transistor and the second n-channel type MOS transistor by the substrate bias effect, making it possible to avoid a slowdown in output signal variation.
A level conversion circuit according to a second aspect of the invention under the present application has a first circuit comprising a first input terminal for receiving a first signal having a first signal amplitude, a first output terminal for supplying a second signal having a second signal amplitude greater than the first signal amplitude and being in the same phase as the first signal, and a second output terminal for supplying a third signal having a second signal amplitude greater than the first signal amplitude and being in the phase reverse to the first signal; and a second circuit for forming a fourth signal having the second signal amplitude on the basis of a variation of the second signal supplied from the first output terminal of the first circuit or of the third signal supplied from the second output terminal of the first circuit, whichever is faster in signal level change, and supplying the fourth signal from the third output terminal, wherein the second circuit receives the second signal or the third signal supplied from the first circuit and a signal in the reverse phase thereto, and the logical threshold is varied so as to accelerate the variation of the fourth signal according to the direction of signal variation.
As the above-described means causes the logical threshold to vary so as to accelerate the variation of the fourth signal according to the direction of signal variation, the output signal is enabled to quickly vary not only at the leading edge but also the trailing edge of the input signal, so that a signal having a small amplitude can be converted into one of a large amplitude and transmitted without sacrificing the signal transmission speed.
Preferably, the second circuit may have a first p-channel type MOS transistor, a second p-channel type MOS transistor, a first n-channel type MOS transistor and a second n-channel type MOS transistor whose source-drain routes are connected in series between the first voltage terminal and the second voltage terminal, wherein the drain of the first p-channel type MOS transistor and the drain of the n-channel type MOS transistor are connected to the third output terminal, high resistance elements may be connected respectively in parallel to the second p-channel type MOS transistor and the first n-channel type MOS transistor, and a delay means is provided to delay the second signal supplied from the first output terminal of the first circuit or the third signal supplied from the second output terminal of the first circuit to control the second p-channel type MOS transistor and the first n-channel type MOS transistor or the first p-channel type MOS transistor and the second n-channel type MOS transistor.
This configuration makes it possible to reduce the gate size of the second p-channel type MOS transistor or the first n-channel type MOS transistor, thereby alleviating the load on the preceding circuit and accelerate the variations of the second signal and the third signal. At the same time, it makes possible shifting of the first p-channel type MOS transistor and the second n-channel type MOS transistor to an on/off state without delay after the fourth signal supplied from the second circuit varies and preparing for the next signal variation.
A level conversion circuit according to a third aspect of the invention under the present application has a first circuit comprising a first input terminal for receiving a first signal having a first signal amplitude, a first output terminal for supplying a second signal having a second signal amplitude greater than the first signal amplitude and being in the same phase as the first signal, and a second output terminal for supplying a third signal having a second signal amplitude greater than the first signal amplitude and being in the phase reverse to the first signal; and a second circuit for forming a fourth signal having the second signal amplitude on the basis of a variation of the second signal supplied from the first output terminal of the first circuit or of the third signal supplied from the second output terminal of the first circuit, whichever is faster in signal level change, and supplying the fourth signal from the third output terminal, wherein, a circuit from which, according to a signal inputted to the gate terminal of a MOS transistor, a signal matching the gate input signal is supplied from the source or drain terminal of the MOS transistor being defined to be one stage, the number of circuit stages which a signal reaching the third output terminal of the second circuit from the first input terminal of the first circuit via the second output terminal goes through and the number of circuit stages which a signal reaching the third output terminal of the second circuit from the first input terminal of the first circuit via the third output terminal goes through are not more than four each.
As in the above-described means the second circuit forms an output signal on the basis of what is faster in signal level change out of the complementary signals supplied from the first circuit and supplies it, the output signal can quickly vary not only at the leading edge but also the trailing edge of the input signal, and a signal having a small amplitude can be converted into one of a large amplitude and transmitted without sacrificing the signal transmission speed. Moreover, as the number of circuit stages which a signal reaching the third output terminal of the second circuit from the first input terminal of the first circuit via the second output terminal goes through and the number of circuit stages which a signal reaching the third output terminal of the second circuit from the first input terminal of the first circuit via the third output terminal goes through are not more than four each, signal transmission is accomplished at higher speed.
A level conversion circuit according to a fourth aspect of the invention under the present application has a first circuit comprising a first input terminal for receiving a first signal having a first signal amplitude, a first output terminal for supplying a second signal having a second signal amplitude greater than the first signal amplitude and being in the same phase as the first signal, and a second output terminal for supplying a third signal having a second signal amplitude greater than the first signal amplitude and being in the phase reverse to the first signal; and a second circuit for forming a fourth signal having the second signal amplitude on the basis of a variation of the second signal supplied from the first output terminal of the first circuit or of the third signal supplied from the second output terminal of the first circuit, whichever is faster in signal level change, and supplying the fourth signal from the third output terminal, wherein, a circuit from which, according to a signal inputted to the gate terminal of a MOS transistor, a signal matching the gate input signal is supplied from the source or drain terminal of the MOS transistor being defined to be one stage, the number of circuit stages which a signal reaching the third output terminal of the second circuit from the first input terminal of the first circuit via the second output terminal goes through and the number of circuit stages which a signal reaching the third output terminal of the second circuit from the first input terminal of the first circuit via the third output terminal goes through are three each.
As in the above-described means the second circuit forms an output signal on the basis of what is faster in signal level change out of the complementary signals supplied from the first circuit and supplies it, the output signal can quickly vary not only at the leading edge but also the trailing edge of the input signal, and a signal having a small amplitude can be converted into one of a large amplitude and transmitted without sacrificing the signal transmission speed. Moreover, as the number of circuit stages which a signal reaching the third output terminal of the second circuit from the first input terminal of the first circuit via the second output terminal goes through and the number of circuit stages which a signal reaching the third output terminal of the second circuit from the first input terminal of the first circuit via the third output terminal goes through are three each, signal transmission is accomplished at even higher speed.
According to a fifth aspect of the invention under the present application, there is provided a semiconductor integrated circuit wherein signals are transmitted in a first amplitude in internal circuits and signals are transmitted and received to and from other external devices in a second amplitude greater than the first amplitude, and a level conversion circuit having any of the above-described configurations is provided in an input/output (I/O) circuit connected to an external terminal at which signals of the second amplitude are supplied. This makes it possible to increase the operating speed of a system using a semiconductor integrated circuit which operates internally at high speed with signals of a smaller amplitude and transmits and receives data to and from other devices with signals of a larger amplitude.
Preferably, an inverse level conversion circuit for converting signals of the second amplitude into signals of the first amplitude may be provided in the I/O circuit connected to the external terminal to which the signals of the second amplitude are inputted. This enables signals of the larger amplitude supplied from other devices to be converted into signals of the smaller amplitude suitable for internal circuits and to be supplied as such to the internal circuits.
According to a sixth aspect of the invention under the present application, there are provided a first level conversion circuit provided with a first circuit comprising a first input terminal for receiving a first signal having a first signal amplitude, a first output terminal for supplying a second signal having a second signal amplitude greater than the first signal amplitude and being in the same phase as the first signal, and a second output terminal for supplying a third signal having a second signal amplitude greater than the first signal amplitude and being in the phase reverse to the first signal; and a second circuit for forming a fourth signal having the second signal amplitude on the basis of a variation of the second signal supplied from the first output terminal of the first circuit or of the third signal supplied from the second output terminal of the first circuit, whichever is faster in signal level change, and supplying the fourth signal from the third output terminal; and a second level conversion circuit consisting of a circuit of the same form as the first circuit. As the second level conversion circuit consists of a smaller number of constituent elements than the first level conversion circuit, both higher speed and smaller occupied space can be achieved at the same speed by selectively using the first level conversion circuit and the second level conversion circuit according to the required signal transmission speed.
Preferably, the first level conversion circuit may be provided on the path of transmitting usual operational signals and the second level conversion circuit, on the path of transmitting testing signals. Since testing signals do not require particularly high transmission speed, arrangement of the second level conversion circuit on the path of transmitting testing signal would contribute to reducing the space occupied.